ISL12022MIBZ-T7A【PDF 28/31 页】IC RTC/CALENDAR TEMP SNSR 20SOIC

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Sheet目录2001

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ISL12022M

FN6668.9

June 20, 2012

OSCILLATOR ACCURACY

ΔFoutI

Oscillator Initial Accuracy

VDD = 3.3V

-2

ppm

6, 17

ΔFoutR

Oscillator Accuracy after Reflow Cycle

VDD = 3.3V

±5

ppm

6, 17

ΔFoutT

Oscillator Stability vs Temperature

VDD = 3.3V

±2

ppm

6, 18

ΔFoutV

Oscillator Stability vs Voltage

2.7V

≤ VDD ≤ 5.5V

-3

ppm

Temp

Temperature Sensor Accuracy

VDD = VBAT = 3.3V

±2

°C

IRQ/FOUT (OPEN DRAIN OUTPUT)

VOL

Output Low Voltage

VDD = 5V, IOL = 3mA

0.4

VDD = 2.7V, IOL = 1mA

0.4

DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface

limits apply over the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 7)

TYP

(Note 8)

MAX

(Note 7)

UNITS

NOTES

Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 7)

TYP

(Note 8)

MAX

(Note 7)

UNITS

NOTES

VDDSR-

VDD Negative Slew Rate

V/ms

VDDSR+

VDD Positive Slew Rate, minimum

0.05

V/ms

I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +85°C.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 7)

TYP

(Note 8)

MAX

(Note 7)

UNITS

NOTES

VIL

SDA and SCL Input Buffer LOW

Voltage

-0.3

0.3 x VDD

VIH

SDA and SCL Input Buffer HIGH

Voltage

0.7 x VDD

VDD + 0.3

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x VDD

V13, 14

VOL

SDA Output Buffer LOW Voltage,

Sinking 3mA

VDD = 5V, IOL = 3mA

0.02

0.4

CPIN

SDA and SCL Pin Capacitance

TA = +25°C, f = 1MHz,

VDD = 5V, VIN =0V, VOUT = 0V

13, 14

fSCL

SCL Frequency

400

kHz

tIN

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the

max spec is suppressed.

tAA

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing

30% of VDD, until SDA exits

the 30% to 70% of VDD

window.

900

tBUF

Time the Bus Must be Free Before

the Start of a New Transmission

SDA crossing 70% of VDD

during a STOP condition, to

SDA crossing 70% of VDD

during the following START

condition.

1300

tLOW

Clock LOW Time

Measured at the 30% of VDD

crossing.

1300

tHIGH

Clock HIGH Time

Measured at the 70% of VDD

crossing.

600

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